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DNPCIE_10G_7K_LL

DNPCIE_10G_7K_LL

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2018-06-26 浏览次数: 2743
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The DNPCIe_10G_K7_LL is a PCIe-based FPGA board designed to minimize input to output processing latency on 10Gb Ethernet packets. The primary application is for ultra low latency, high throughput trading without CPU intervention. Every possible variable that affects input to output latency has been analyzed and minimized. Raw 10 GbE Ethernet packets can be analyzed and acted upon without interrupts or an operating system adding delay to the process. This configurable hardware computing platform has the ability to achieve the theoretical minimum Ethernet packet processing latency.

1. The FPGA – Xilinx Kintex-7

We use a single FPGA from the Xilinx Kintex-7 in the FFG676 package. This package supports 400 I/O with the majority utilized. Most are dedicated to off chip memory peripherals including a single QDR II+ for low-latency, high speed look-up, and DDR3 Mini-DIMM for performance oriented bulk storage. The Kintex-7 FPGA contains high-speed transceivers capable of 10GbE without need for an external PHY. Four of these transceivers are used for 4-lanes of GEN2-capable PCIe. Two of the transceivers are connected to 10 GbE SFP+ sockets.  

Two possible FPGAs can be stuffed: 7K410T or the 7K325T. Both FPGAs come in a variety of speed grades (-1,-2/2L, -3) with -3 being the fastest. The -1 speed grade is not rated for 10 GbE transceiver operation, so isn't applicable to this application.  and  the DNPCIe_10G_K7_LL_QSFP contains all of the basic functions required to minimize the amount of time it takes to receive Ethernet packets, process them, and respond deterministically. By using the FPGA to process Ethernet packets, the processor and operating system are removed from the critical path and traditional sources of latency such as interrupts and context switching no longer hinder performance. Not a single clock cycle. For algorithms requiring processing, FPGA resources can be hard coded to perform the task, including real-time Monte Carlo analysis and floating point. This makes DNPCIe_10G_K7_LL specifically suitable for compliance checking, high frequency trading, low latency trading, derivative pricing and risk management.

Specs of FPGAs Available on the DNPCIe_10G_K7_LL


l 2 separate 10GbE LAN/WAN using SFP+ modules  

Ø Customized IP for packet analysis with minimum latency

l   Hosted in a an 4-lane GEN1 or GEN2 PCIe slot

Ø  Compatible with 

Ø  Compatible with 

Ø  16-lane mechanical

Ø Low profile, short length form factor

l    Fully compatible with our OPTIONAL TCP Offload Engines (/)

l    OPTIONAL FIX board support package (). Functioning reference design with:

Ø  10-Gigabit Ethernet MAC

Ø  TCP/IP Offload Engine (TOE)

Ø  FIX protocol parser

Ø  Tick Filter (optional)

Ø   (4-lane, GEN2)

Ø  Memory

l  QDR2 II+ Controller

l  DDR3 Controller

l    Xilinx Kintex-7 FPGA (FFG676) :

Ø  7K410T-3,-2,-2L (fastest to slowest)

Ø  7K325T-3,-2,-2L

Ø  3M ASIC gates (ASIC measure) when stuffed with Kintex-7 7K410T

l  254k flip-flop/6-input LUTs (708k total FFs)

l  3.578 Kbytes total FPGA block memory (1590, 18 kbit blocks)

l  1540, 25x18 multipliers

l    Bulk memory: DDR3 Mini-uDIMM

Ø  72-bit data width (64-bit with 8-bit ECC)

Ø  666.5MHz operation, PC3-10600 (single rank)

Ø  800MHz operation, 1600Mb/s, PC3-12800 (single rank)

Ø  Addressing/power to support 4GB

Ø  DDR3 Verilog/VHDL reference design provided (no charge)

l  Optimized DDR3 controller for lowest latency bulk memory access

Ø Optional RLDRAM Mini-DIMM instead of DDR3 for ultra low latency

l    QDRII+ SRAM memory: 4M x 18 (72Mb)

Ø  Separate 18-bit read and write ports

Ø  500 MHz bus operation, DDR (double data rate)

l  Fast enough to be clocked at 312.50 MHz

l  Eliminates clock synchronization delays between memory and Ethernet clock

l    SMBus-based thermal management

l    GPS input for precise message time stamping and tracking

l    Full support for embedded logic analyzers via JTAG interface

Ø  ChipScope and other third-party debug solutions:

l  Mentor Graphics, SpringSoft

l    Noninvasive debug via FPGA register readback: 

l    FPGA-controlled Status LEDs

Ø  Enough light to make your houseplants happy.


联系我们

  • 025-58800523

    电话:025-58800523

  •  sales@

    邮箱:sales@

  • 南京市高新区星火路17号集成电路产业中心B座1003

    地址:南京市高新区星火路17号集成电路产业中心B座1003

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